4. Wie schnell und einfach unter Linux kompilieren?

Wie schnell und einfach unter Linux kompilieren?

  • K

    Wie kann ich am einfachsten Weg das Kompilierungsprozess unter Linux schneller machen? Ich kann nicht immer wieder meine Kompiler-Flags aufzählen usw.

    0
  • M

    make ober boost-build benutzen zB? oder scons etc.

    0
  • K

    Wie benutzt man make?

    0
  • L

    Mit 'nem MAKEFILE...

    Sonst schreib dir doch ein eigenes shellscript...

    0
  • B

    Feunde dich mit Makefiles an. Schadet nicht.

    0
  • K

    Ja, das mach ich 😉

    0
  • R

    Ein guter Einstieg ist sicher die ultimative Makefile

    0
  • K

    rüdiger schrieb:

    Ein guter Einstieg ist sicher die ultimative Makefile

    Danke. Das habe ich gerade gelesen. Ich habe mir selbst so was gebastelt. Leider funktioniert es nicht wie es soll...
    Hier ist die Makefile-Datei:

    # define a sample name for the application's name
target := app

# define build options
# compiler name
CXX := g++
# compile options
CXXFLAGS :=
# link options
LDFLAGS :=
# link libraries
LDLIBS :=

# construct list of .cpp and their corresponding .o and .d files
sources := $(wildcard *.cpp)
objects := $(sources:.cpp =.o)
dependencies := $(sources:.cpp=.d)

# include all .d files only when 'make clean' is not specified
# this is done to prevent recreating .d files when the clean target is specified
# if no dependencies exist, on the other hand, no warning will be issued:'-' key
ifneq ($(MAKECMDGOALS), clean)
-include $(dependencies)
endif

# main goal for 'make' is the first target, here 'all'
# 'all' is always assumed to be a target, and not a file
# file disambiguity is achieved via the '.PHONY' directive
# usage: 'make all' or simply 'make', since this is the first target
.PHONY : all
all : $(target)

# rule for 'target'
# the automatic variable '$<' expands to the first prerequisite (objects)
# the automatic variable '$@' expands to the target's name
# the actual action done is the linking of all .o files into the executable
$(target) : $(objects) $(dependencies)
	$(CXX) $(LDFLAGS) $< $(LDLIBS) -o $@

# rule for creating .o files out of a corresponding .cpp and .d file
%.o : %.cpp %.d
	$(CXX) -c $(CXXFLAGS) $< -o $@

# rule for creating .d files out of a corresponding .cpp file
%.d : %.cpp
	$(CXX) -E -MM $< -o $@

# even if there exists a file 'clean', 'make clean' will execute its commands
# and won't ever assume 'clean' is an up-to-date file
# the 'clean' target will remove all intermediate files - .o and .d respectively
# usage: 'make clean'
.PHONY : clean
clean :
	rm -f $(target) $(dependencies) $(objects)

    Es wird kein app Programm erstellt, sondern nur .d und .o Datei. Auch beim clean wird die .cpp Datei gelöscht. Warum? Was mache ich so falsch?

    Und noch 'ne Frage! Bei include, wird make für die anderen .d Dateien hervorgerufen. Aber wie kann ich ihn die CXX und CXXFLAGS übergeben? Sonst hat es keinen Sinn...

    0
  • K

    Das Problem wurde gelöst:

    # define a sample name for the application's name
target := app

# define build options
# compiler name
CXX := g++
# compile options
CXXFLAGS := -ansi -std='c++98' -pedantic -Wall -Weffc++ -Wold-style-cast \
-Wextra -Wunknown-pragmas -Wshadow -Wwrite-strings -Wconversion \
-Wunreachable-code -Winline -Wdisabled-optimization -O3 -march=prescott \
-mfpmath=sse -mmmx -msse -msse2 -msse3
# link options
LDFLAGS := -s
# link libraries
LDLIBS :=

# construct lists of .cpp and their corresponding .o files
sources := $(wildcard *.cpp)
objects := $(sources:.cpp=.o)
dependency := Makefile.dep

# main goal for 'make' is the first target, here 'all'
# 'all' is always assumed to be a target, and not a file
# file disambiguity is achieved via the '.PHONY' directive
# usage: 'make all' or simply 'make', since this is the first target
.PHONY : all clean
all : $(target)
	@echo done.

# rule for 'target'
# the automatic variable '$^' expands to all prerequisites (objects)
# the automatic variable '$@' expands to the target's name
# the actual action done is the linking of all .o files into the executable
$(target) : $(objects)
	@echo linking...
	@$(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $@

# rule for creating an .o file out of a corresponding .cpp file
# the automatic variable '$<' expands to the first prerequisite (%.cpp)
.cpp.o :
	@$(CXX) -c $(CXXFLAGS) $< -o $@

# include the dependency file only when 'make clean' is not specified
# this is done to prevent recreating it when the clean target is specified
# if no dependency exist, on the other hand, no warning will be issued:'-' key
ifneq ($(MAKECMDGOALS), clean)
-include $(dependency)
endif

# rule for creating a dependency file
# the preprocessor is used to find out all header-dependencies and store them
# in a dependency file, later to be analyzed by the 'make' utility
$(dependency) :
	@echo generating dependencies...
	@$(RM) $(dependency)
	@$(CXX) -E -MM $(sources) >> $(dependency)
	@echo compiling...

# even if there exists a file 'clean', 'make clean' will execute its commands
# and won't ever assume 'clean' is an up-to-date file
# the 'clean' target will remove all intermediate files - .o, .dep respectively
# usage: 'make clean'
clean :
	@$(RM) $(target) $(dependency) $(objects)
	@echo target, dependencies and objects were removed
    0
Anmelden zum Antworten